1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly, to chemical mechanical polishing (CMP) using feedback control of polish buff time as a function of post-buff scratch count.
2. Description of the Related Art
CMP is a widely used means of planarizing silicon dioxide as well as other types of processing layers on semiconductor wafers. Chemical mechanical polishing typically utilizes an abrasive slurry disbursed in an alkaline or acidic solution to planarize the surface of the wafer through a combination of mechanical and chemical action. Generally, a chemical mechanical polishing tool includes a polishing device positioned above a rotatable circular platen or table on which a polishing pad is mounted or above a semi-rigid linearly-moving belt on which a polishing pad is mounted. The polishing device may include one or more rotating carrier heads to which wafers may be secured, typically through the use of vacuum pressure. In use, the platen may be rotated and an abrasive slurry may be dispersed onto the polishing pad. Once the slurry has been applied to the polishing pad, a downward force may be applied to each rotating carrier head to press the attached wafer against the polishing pad. As the wafer is pressed against the polishing pad, a surface of a process layer formed above the wafer is mechanically and chemically polished.
As the size of semiconductor devices is scaled down, the importance of chemical mechanical polishing to the fabrication process increases. In particular, it becomes increasingly important to minimize surface damage, such as microscratching, to either a postpolish surface of a process layer, or if the process layer is completely removed during the polishing process, to any underlying material residing beneath the polished process layer, such as another process layer. For example, in one embodiment, during a CMP process, abrasive particles within the slurry may be used to mechanically abrade a polishing surface of a process layer that has been formed above the wafer. As the wafer is polished, the interaction between the polishing surface and the abrasive particles may produce undesirable surface damage (e.g., microscratches) to the post-polish surface of the process layer.
In one illustrative embodiment, an oxide layer of a wafer may be planarized using a conventional CMP process (i.e., the surface of the oxide layer may be polished to produce a more uniform layer of material.) During this process, the interaction between the abrasive particles within the slurry and the surface of the oxide layer may produce undesirable surface damage, such as microscratches, in the polished surface of the oxide layer. Moreover, the severity of the surface damage may depend upon, among other things, the processing parameters of the polishing process (e.g., polishing time, slurry composition, carrier arm down force, etc.) Additionally, changes in polishing process consumables, such as slurry particle distribution, polishing pad wear, and the like, may also contribute to damaging a surface of a process layer. If not removed, microscratches or other types of surface damage may xe2x80x9ctrapxe2x80x9d portions of additional process layers within the oxide layer during subsequent processing steps.
For example, once the polishing of the oxide layer is complete, depending upon the particular process, additional process layers may be formed on the polished surface of the oxide layer. With one exemplary process, a conductive layer of material, such as metal, may be deposited on the polished surface of the oxide layer. As with conventional processing, the metal processing layer may be patterned, etched, and/or polished to produce at least a portion of a desired integrated circuit feature or configuration. For example, a blanket metal layer comprised of tungsten or copper may be formed above openings in the oxide layer and then subsequently polished to form electrical paths (e.g., interconnects) between stacked processing layers. Unfortunately, if microscratches are present in the polished surface of the oxide layer, portions of the metal processing layer may become xe2x80x9ctrappedxe2x80x9d within the oxide layer, which may result in poor performance of the finished semiconductor device. For example, the xe2x80x9ctrappedxe2x80x9d portion of the metal layer may produce a short circuit condition within the finished device or, in a less extreme case, undesirably high electrical leakage currents between adjacent metal lines.
One conventional method for alleviating polishing induced damage to the surface of a wafer or a process layer is post-polish buffing. For example, once the CMP process is complete, the post-polish surface of the process layer may be processed through a xe2x80x9cbuffxe2x80x9d step, which may at least partially reduce the severity of any surface damage. Additionally, if the polished process layer is substantially removed during the polishing process, the underlying material (e.g., wafer, additional process layer, etc.) may be at least partially exposed to the polishing process. If this occurs, the underlying material may be processed through the xe2x80x9cbuffxe2x80x9d step to remove any surface damage that may have occurred during exposure to the polishing process. In one embodiment, the xe2x80x9cbuffxe2x80x9d step comprises positioning the polished surface of a process layer or the exposed underlying material against a rotating buffing pad that has been mounted to a platen. During this process, surface damage, such as microscratches, may be at least partially eliminated by slowly removing a portion of the process layer resulting in a substantially defect free post-buff surface.
The duration of the buff process may be limited by the thickness of the material being processed. For example, in one embodiment, a layer of silicon dioxide may be used as an electrically insulating layer between stacked metal process layers that have been formed above a surface of a wafer. To provide sufficient electrical isolation, a minimum thickness of the oxide layer may be required to prevent cross-talk or other signal disturbances between the stacked metal process layers. Because the post-polish buff process may remove a portion of the material being processed, a compromise is typically made between removing surface defects and maintaining a minimum thickness of the process layer.
Additionally, the duration of the buff process may be limited by increases in the surface non-uniformity of the process layer. In some application, increasing the duration of the buff process may undesirably increase the variability in thickness of the material being processed, thus, resulting in increased surface non-uniformity of a process layer. To prevent unreasonable increases in surface non-uniformity, a compromise is typically made between removing surface defects and preventing increases in surface non-uniformity.
Typically, the duration of the buff step is a process parameter that is part of an overall predetermined polish recipe. Currently, process engineers and other technicians have limited ability to adjust the duration of a post-polish buff process. Moreover, determining the duration of the post-polish buff process is exacerbated by the interrelation of the processing parameters involved, such as process layer thickness, defect density, surface non-uniformity, and the like.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided. The method includes providing a first wafer having at least one process layer formed thereon. A portion of a first process layer is removed using a polishing process. A portion of at least one of the first process layer and a second process layer is removed using a buffing process for a pre-selected duration of time. A buffed surface of at least one of the first process layer and the second process layer is inspected to determine a post-buff defect density for the inspected process layer. The duration of the buffing process is adjusted for a second wafer based on the determined post-buff defect density of the inspected process layer.
In another aspect of the present invention, a system is provided. The system includes a processing tool, at least one metrology tool, and a process controller. The processing tool is adapted to remove at least a portion of a first process layer of a first wafer using a buffing process for a pre-selected duration of time. The at least one metrology tool is adapted to determine a post-buff defect density of at least one of the first process layer and a second process layer. The process controller is coupled to at least one of the processing tool and the at least one metrology tool. The process controller is adapted to receive the determined postbuff defect density from the at least one metrology tool, and adjust the duration of the buffing process for a second wafer based on the determined post-buff defect density of the first wafer.